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| datasheet r01ds0207ej0100 rev.1.00 apr 15, 2013 page 1 of 28 r01ds0207ej0100 rev.1.00 apr 15, 2013 rl78/g10 renesas mcu true low power platform (as low as 46 a/mhz), 2.0 to 5.5v operation, 1 to 4 kbyte flash for general purpose applications 1. outline 1.1 features ultra-low power technology ? 2.0 to 5.5 v operation from a single supply ? stop (ram retained): 0.56 a ? operating: 46 a /mhz rl78-s1 core ? instruction execution: 78 % of instructions can be executed in 1 to 2 clock cycles ? cisc architecture (harvard) with 3-stage pipeline ? multiply: 8 x 8 to 16-bit result in 2 clock cycles ? 16-bit barrel shifter for shift & rotate in 2 clock cycle ? 1-wire on-chip debug function main flash memory ? density: 1 to 4 kbyte ? flash memory rewritable voltage: 4.5 to 5.5 v ram ? 128 to 512 byte size options ? supports operands or instructions ? back-up retention in all modes high-speed on-chip oscillator ? 20 mhz with +/-2 % accuracy over voltage (2.0 to 5.5 v) and temperature (-20 to +85c) ? pre-configured settings: 20 mhz, 10 mhz, 5 mhz, 2.5 mhz, and 1.25 mhz reset and supply management ? selectable power-on reset (spor) generator with 4 setting options multiple communication interfaces ? 1 x i 2 c master ? 1 x i 2 c multi-master (only for 16-pin product) ? 1 x uart (7-, 8-bit) ? up to 2 x csi/spi (7-, 8-bit) extended-function timers ? multi-function 16-bit timers: up to 4 channels ? interval timer: 12-bit, 1 channel (only for 16-pin product) ? 15 khz watchdog timer : 1 channel rich analog ? adc: up to 8 channels, 10-bit resolution, 3.4 s conversion time ? supports 2.4 v ? 1 x comparator (only for 16-pin product) safety features ? detects execution of illegal instruction ? detects watchdog timer program loop general purpose i/o ? high-current (up to 20 ma per pin) ? open-drain, internal pull-up support external interrupt ? external interrupt input: 4 ? key interrupt input: 6 operating ambient temperature ? standard: -40 to +85c package type and pin count ? ssop: 10 and 16 pin * there is difference in specifications between every product. please refer to specification for details.
rl78/g10 chapter 1 outline r01ds0207ej0100 rev.1.00 apr 15, 2013 page 2 of 28 ? rom, ram capacities flash rom ram 10 pins 16 pins 4 kb 512 b ? r5f10y47asp note 2 2 kb 256 b r5f10y16asp r5f10y46asp note 2 1 kb 128 b r5f10y14asp r5f10y44asp note 2 notes 1. 16-pin products only 2. under development remark the functions mounted de pend on the product. see 1.6 outline of functions . rl78/g10 chapter 1 outline r01ds0207ej0100 rev.1.00 apr 15, 2013 page 3 of 28 1.2 list of part number figure 1-1. classification of part number part no. r 5 f 1 0 y 1 7 a x x x s p #v0 package type: packaging style rom number (omitted with blank products) rom capacity: rl78/g10 group: 10y renesas mcu renesas semiconductor product sp : ssop, 0.65 mm pitch 4 : 1 kb 6 : 2 kb 7 : 4 kb #v0 : tray #x0 : embossed tape pin count: 1 : 10-pin 4 : 16-pin classification: a : consumer applications, operating ambient temperature : -40 c to 85 c memory type: f : flash memory pin count package part number r5f10y16asp#v0, r5f10y16asp#x0 10 pins 10-pin plastic lssop (4.4 3.6 mm, 0.65mmpitch) r5f10y14asp#v0, r5f10y14asp#x0 r5f10y47asp note r5f10y46asp note 16 pins 16-pin plastic ssop (4.4 5.0 mm, 0.65mmpitch) r5f10y44asp note note under development caution the part number re presents the number at the time of publication. be sure to review the latest part number through the target pr oduct page in the renesas electronics corp.website. rl78/g10 chapter 1 outline r01ds0207ej0100 rev.1.00 apr 15, 2013 page 4 of 28 1.3 pin configuration (top view) 1.3.1 10-pin products ? 10-pi n plastic lssop (4.4 3.6) 10 9 8 7 6 1 2 3 4 5 p04/ani3/ti01/to01/kr5 p03/ani2/to00/kr4/(intp1) p02/ani1/sck00/scl00/pclbuz0/kr3 p01/ani0/si00/rxd0/sda00/kr2 p00/so00/txd0/intp1 p40/kr0/tool0/(pclbuz0)/(ti01/to01) p125/kr1/reset p137/ti00/intp0 v ss v dd remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). 1.3.2 16-pin products ? 16-pi n plastic ssop (4.4 5.0) 1 2 3 4 5 p41/ti03/intp2 p40/kr0/tool0/(pclbuz0)/(ti01/to01) p125/kr1/reset p137/ti00/intp0 p122/x2/exclk/(intp2) p121/x1/(intp3) v ss v dd 6 7 8 16 15 14 13 12 11 10 9 p07/sdaa0/to03/ani6/sck01 p06/scla0/intp3/ani5/si01 p05/ani4/ti02/to02/so01 p04/ani3/ti01/to01/kr5/ivref0 p03/ani2/to00/kr4/(intp1)/ivcmp0 p02/ani1/sck00/scl00/pclbuz0/kr3/vcout0 p01/ani0/si00/rxd0/sda00/kr2 p00/so00/txd0/intp1 remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g10 chapter 1 outline r01ds0207ej0100 rev.1.00 apr 15, 2013 page 5 of 28 1.4 pin identification ani0 to ani6 : analog input intp0 to intp3 : external interrupt input kr0 to kr5 : key return p00 to p07 : port 0 p40, p41 : port 4 p121, p122, p125 : port 12 p137 : port 13 pclbuz0 : programmable clock output/ buzzer output exclk : external clock input x1, x2 : crystal oscillator ivcmp0 : comparator input vcout0 : comparator output ivref0 : comparator reference input reset : reset rxd0 : receive data sck00, sck01 : serial clock input/output scl00, scla0 : serial clock output sda00, sdaa0 : serial data input/output si00, si01 : serial data input so00, so01 : serial data output ti00 to ti03 : timer input to00 to to03 : timer output tool0 : data input/output for tool txd0 : transmit data v dd : power supply v ss : ground rl78/g10 chapter 1 outline r01ds0207ej0100 rev.1.00 apr 15, 2013 page 6 of 28 1.5 block diagram 1.5.1 10-pin products port 0 p00 to p04 port 4 p40 port 12 p125 5 pclbuz0 clock generator + reset generator reset t ool0 sau0 (1 ch) ch01 ch00 tau0 (2 ch) uart0 on-chip debugger rl78-s1 interrupt control interrupt control 2 ch buzzer/clock output control key return 6 ch bcd adjustment selectable power-on- reset low-speed on-chip oscillator 15 khz high-speed on-chip oscillator 1.25 to 20 mhz iic00 csi00 scl00 sda00 rxd0 txd0 sck00 si00 so00 6 2 kr0 to kr5 intp0, intp1 ani0 to ani3 low-speed on-chip oscillator watchdog timer 8-/10-bit a/d converter 4 ch port 13 p137 ti00 /to00 ti01 /to01 ram 256 b code flash: 2 kb v dd v ss rl78/g10 chapter 1 outline r01ds0207ej0100 rev.1.00 apr 15, 2013 page 7 of 28 1.5.2 16-pin products port 0 p00 to p07 port 4 port 12 p121, p122, p125 8 buzzer/clock output control pclbuz0 clock generator + reset generator reset on-chip tool0 bcd adjustment on-chip debugger high-speed on-chip oscillator 1.25 to 20 mhz low-speed on-chip oscillator 15 khz selectable power-on- reset sau0 (1 ch) uart0 iic00 scl00 sda00 rxd0 txd0 6 4 key return 6 ch kr0 to kr5 intp0 to intp3 ani0 to ani6 low-speed on-chip oscillator port 13 p137 8-/10-bit a/d converter 8 ch interrupt control 4 ch watchdog timer rl78-s1 interrupt control ram 512 b code flash: 4 kb v dd v ss p40, p41 2 3 x1 x2/exclk main osc 1 to 20 mhz iica0 scla0 sdaa0 comp ivcmp0 ivref0 vcout0 12-bit interval timer csi01 csi00 so01 si00 tau0 (4 ch) ch03 ch01 ch00 ch02 ti01 / to01 ti02 / to02 ti03 / to03 sck00 so00 si01 sck01 ti00 / to00 rl78/g10 chapter 1 outline r01ds0207ej0100 rev.1.00 apr 15, 2013 page 8 of 28 1.6 outline of functions this outline describes the fu nction at the time when peripheral i/o redi rection register (pior) is set to 00h. 10-pin 16-pin item r5f10y16asp r5f10y14asp r5f10y47asp r5f10y46asp r5f10y44asp code flash memory 2 kb 1 kb 4 kb 2 kb 1 kb ram 256 b 128 b 512 b 256 b 128 b high-speed system clock ? x1, x2 (crystal/ceramic) oscillation, external main system clock input (exclk): 1 to 20 mhz: v dd = 2.7 to 5.5 v 1 to 5 mhz: v dd = 2.0 to 5.5 v main system clock high-speed on-chip oscillator clock ? 1.25 to 20 mhz (v dd = 2.7 to 5.5 v) ? 1.25 to 5 mhz (v dd = 2.0 to 5.5 v) low-speed on-chip oscillator clock 15 khz (typ) general-purpose register 8-bit register 8 minimum instruction execution time 0.05 s (20 mhz operation) instruction set ? data transfer (8 bits) ? adder and subtractor/logical operation (8 bits) ? multiplication (8 bits 8 bits) ? rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. total 8 14 cmos i/o 6 (n-ch open-drain output (v dd tolerance): 2) 10 (n-ch open-drain output (v dd tolerance): 4) i/o port cmos input 2 4 16-bit timer 2 channels 4 channels watchdog timer 1 channel 12-bit interval timer ? 1 channel timer timer output 2 channels (pwm output: 1) 4 channels (pwm outputs: 3 note 1 ) 1 clock output/buzzer output 2.44 khz to 10 mhz: (peripheral hardware clock: f main = 20 mhz operation) comparator ? 1 8-/10-bit resolution a/d converter 4 channels 8 channels serial interface [10-pin prod ucts] csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel [16-pin products] csi: 2 channels/simplified i 2 c: 1 channel/uart: 1 channel i 2 c bus ? 1 channel internal 8 14 vectored interrupt sources external 3 5 key interrupt 6 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by selectable power-on-reset ? internal reset by illegal instruction execution note 2 ? internal reset by data retention lower limit voltage selectable power-on-reset circuit detection voltage: 2.0 v/2.4 v/2.7 v/4.0 v on-chip debug function provided power supply voltage v dd = 2.0 to 5.5 v operating ambient temperature t a = - 40 to + 85 c rl78/g10 chapter 1 outline r01ds0207ej0100 rev.1.00 apr 15, 2013 page 9 of 28 notes 1. the number of outputs varies, depending on the setting of channels in use and t he number of the master (see 6.8.3 operation as multiple pwm output function in the rl78/g10 user?s manual ). 2. the illegal instruction is generated when instruction co de ffh is executed. reset by the illegal instruction execution not issued by emulati on with the on-chip debug emulator. rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 10 of 28 2. electrical specifications cautions 1. this chapter explains the electrical specifications of tw o products, the r5f10y16asp and the r5f10y14asp. 2. electrical specifications for the 16-pin produc ts are t. b. d. because these products are under development. 3. the rl78/g10 has an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug func tion in products designated fo r mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability ther efore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 4. the pins mounted depend on the product. refe r to 2.1 port functions and 2.2.1 functions for each product in the rl78/g10 user?s manual. rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 11 of 28 2.1 absolute maximum ratings (t a = 25 c) parameter symbols conditions ratings unit supply voltage v dd ?0.5 to +6.5 v input voltage v i1 ?0.3 to v dd + 0.3 note v output voltage v o1 ?0.3 to v dd + 0.3 v per pin ?40 ma p40 ?40 ma output current, high i oh1 total of all pins -140 ma p00 to p04 ?100 ma per pin 40 ma p40 40 ma output current, low i ol1 total of all pins 140 ma p00 to p04 100 ma operating ambient temperature t a ?40 to +85 c storage temperature t stg ?65 to +150 c note must be 6.5 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even mo mentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage , and therefore the product must be used under conditions that ensure that the absolute maxi mum ratings are not exceeded. remarks 1. unless specified otherwise, the characteristics of alternat e-function pins are the sa me as those of the port pins. 2. the reference voltage is v ss . 2.2 oscillator characteristics 2.2.1 on-chip osc illator characteristics (t a = ? 40 to +85 c, 2.0 v v dd 5.5 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator oscillation clock frequency notes 1, 2 f ih 1.25 20 mhz t a = -20 to +85 c -2.0 +2.0 % high-speed on-chip oscillator oscillation clock frequency accuracy t a = -40 to -20 c -3.0 +3.0 % low-speed on-chip oscillator oscillation clock frequency note 3 f il 15 khz low-speed on-chip oscillator oscillation clock frequency accuracy -15 +15 % notes 1. high-speed on-chip oscillator frequency is select ed by bits 0 to 2 of option byte (000c2h). 2. this only indicates the oscillator characteristics. refe r to ac characteristics for instruction execution time. 3. this only indicates the oscillator characteristics. rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 12 of 28 2.3 dc characteristics 2.3.1 pin characteristics (t a = ? 40 to +85 c, 2.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit p00, p01, p02 to p04, p40 per pin -10.0 note 2 ma 4.0 v v dd 5.5 v -10.0 ma 2.7 v v dd < 4.0 v -2.0 ma p40 total note 3 2.0 v v dd < 2.7 v -1.5 ma 4.0 v v dd 5.5 v -50.0 ma 2.7 v v dd < 4.0 v -10.0 ma p00, p01, p02 to p04 total note 3 2.0 v v dd < 2.7 v -7.5 ma output current, high note 1 i oh1 total of all pins note 3 -60.0 ma p00 to p04, p40 per pin 20.0 note 2 ma 4.0 v v dd 5.5 v 20.0 ma 2.7 v v dd < 4.0 v 3.0 ma p40 total note 3 2.0 v v dd < 2.7 v 0.6 ma 4.0 v v dd 5.5 v 80.0 ma 2.7 v v dd < 4.0 v 12.0 ma p00 to p04 total note 3 2.0 v v dd < 2.7 v 2.4 ma output current, low note 4 i ol1 total of all pins note 3 100.0 ma input voltage, high v ih1 0.8 v dd v dd v input voltage, low v il1 0 0.2 v dd v i oh =-10 ma v dd -1.5 v 4.0 v v dd 5.5 v i oh =-3.0 ma v dd -0.7 v 2.7 v v dd 5.5 v i oh =-2.0 ma v dd -0.6 v output voltage, high note 5 v oh1 2.0 v v dd 5.5 v i oh =-1.5 ma v dd -0.5 v i ol = 20 ma 1.3 v 4.0 v v dd 5.5 v i ol = 8.5 ma 0.7 v i ol = 3.0 ma 0.6 v 2.7 v v dd 5.5 v i ol = 1.5 ma 0.4 v output voltage, low note 6 v ol1 2.0 v v dd 5.5 v i ol = 0.6 ma 0.4 v input leakage current, high i lih1 v i = v dd 1 a input leakage current,low i lil1 v i = v ss -1 a on-chip pull-up resistance r u v i = v ss 10 20 100 k notes 1. value of current at which the device operation is guaranteed even if the current flows from the v dd pin to an output pin. 2. do not exceed the total current value. 3. this is the output current value und er conditions where the duty factor 70%. the output current valu e when the duty factor > 70% can be calculated with the following expression (when changing the duty factor to n%). rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 13 of 28 ? total output current of pins = (i oh 0.7)/(n 0.01) rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 14 of 28 2.3.2 supply current characteristics (t a = ? 40 to +85 c, 2.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit basic operation f ih = 20 mhz v dd = 3.0 v, 5.0 v 0. 91 f ih = 20 mhz v dd = 3.0 v, 5.0 v 1.57 2.04 i dd1 operating mode normal operation f ih = 5 mhz v dd = 3.0 v, 5.0 v 0.85 1.15 ma f ih = 20 mhz v dd = 3.0 v, 5.0 v 350 820 i dd2 note 2 halt mode f ih = 5 mhz v dd = 3.0 v, 5.0 v 2 90 600 a supply current note 1 i dd3 note 3 stop mode v dd = 3.0 v 0.56 2.00 a wdt supply current note 4 i wdt f il = 15 khz 0.31 a v dd = 5.0 v 1.30 1. 90 adc supply current note 5 i adc during conversion at the highest speed v dd = 3.0 v 0.50 ma notes 1 . total current flowing into v dd , including the input leakage current flowin g when the level of the input pin is fixed to v dd or v ss . the values below the max. column include the peripheral operation current. however, not including the current flowing into the watchdog ti mer, a/d converter, i/o port, and on-chip pull-up/pull- down resistors. 2. during halt instruction execution by flash memory. 3. when the high-speed on-chip oscillator is stopped. 4. current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). the current value of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when the watchdog timer operates. 5. current flowing only to the a/d converter. the current value of the rl78 microcont rollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. remarks 1. f il : low-speed on-chip oscillator clock frequency 2. f ih : high-speed on-chip oscillator clock frequency 3. temperature condition of the typ. value is t a = 25 c rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 15 of 28 2.4 ac characteristics (t a = ? 40 to +85 c, 2.0 v v dd 5.5 v, v ss = 0 v) items symbol conditions min. typ. max. unit 2.7 v v dd 5.5 v 0.05 0.8 s instruction cycle (minimum instruction execution time) t cy main system clock (f main ) operation 2.0 v v dd 5.5 v 0.2 0.8 s ti00, ti01 input high-level width, low-level width t tih , t til noise filter is not used 1/f mck + 10 ns 4.0 v v dd 5.5 v 10 mhz 2.7 v v dd < 4.0 v 5 mhz to00, to01 output frequency f to 2.0 v v dd < 2.7 v 2.5 mhz 4.0 v v dd 5.5 v 10 mhz 2.7 v v dd < 4.0 v 5 mhz pclbuz0 output frequency f pcl 2.0 v v dd < 2.7 v 2.5 mhz reset low-level width t rsl 10 s remark f mck : timer array unit operation clock frequency ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol ti/to timing ti00, ti01 t til t tih to00, to01 1/f to rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 16 of 28 interrupt request input timing intp0, intp1 t intl t inth key interrupt input timing kr0 to kr5 t kr reset input timing reset t rsl rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 17 of 28 2.5 serial communication characteristics 2.5.1 serial array unit (1) uart mode (t a = ? 40 to +85 c, 2.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit f mck /6 bps transfer rate theoretical value of the maximum transfer rate f clk = f mck = 20 mhz 3.3 mbps uart mode connection diagram rl78 microcontroller user?s device txd0 rxd0 rx tx uart mode bit width (reference) txd0 1/transfer rate high-/low-bit width baud rate error tolerance rxd0 remark f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 18 of 28 (2) csi mode (master mode, sckp... internal clock output) (t a = ? 40 to +85 c, 2.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit 2.7 v v dd 5.5 v 200 ns sckp cycle time t kcy1 t kcy1 4/f clk 2.0 v v dd 5.5 v 800 ns 2.7 v v dd 5.5 v t kcy1 /2-18 ns sckp high-/low-level width t kh1 , t kl1 2.0 v v dd 5.5 v t kcy1 /2-50 ns 2.7 v v dd 5.5 v 47 ns sip setup time (to sckp ) note 1 t sik1 2.0 v v dd 5.5 v 110 ns sip hold time (from sckp ) note 2 t ksi1 1 9 ns delay time from sckp to sop output note 3 t kso1 c = 30 pf note 4 25 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and c kpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. remarks 1. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bi t of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 1 9 of 28 (3) csi mode (slave mode, sc kp... external clock input) (t a = ? 40 to +85 c, 2.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit f mck = 20 mhz 8/f mck ns 2.7 v v dd 5.5 v f mck 10 mhz 6/f mck ns sckp cycle time t kcy2 2.0 v v dd < 2.7 v 6/f mck ns sckp high-/low-level width t kh2 , t kl2 2.0 v v dd 5.5 v t kcy2 /2 ns 2.7 v v dd 5.5 v 1/f mck + 20 ns sip setup time (to sckp ) note 1 t sik2 2.0 v v dd < 2.7 v 1/f mck + 30 ns sip hold time (from sckp ) note 2 t ksi2 2.0 v v dd 5.5 v 1/f mck + 31 ns 2.7 v v dd 5.5 v 2/f mck + 50 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 2.0 v v dd < 2.7 v 2/f mck + 110 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and c kpmn = 1. the sip set up time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and c kpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sop output lines. remarks 1. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 20 of 28 csi mode connection diagram sck00 so00 sck si si00 so rl78 microcontroller user?s device csi mode serial transfer timing (when dap00 = 0 and ckp00 = 0, or dap00 = 1 and ckp00 = 1.) si00 so00 t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 input data t kso1, 2 output data sck00 rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 21 of 28 (4) simplified i 2 c mode (t a = ? 40 to +85 c, 2.0 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit sclr clock frequency f scl 2.0 v v dd 5.5 v, c b = 100 pf, r b = 3 k 400 note 1 khz hold time when sclr = "l" t low 2.0 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1150 ns hold time when sclr = "h" t high 2.0 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1150 ns data setup time (reception) t su: dat 2.0 v v dd 5.5 v, c b = 100 pf, r b = 3 k 1/f mck + 145 note 2 ns data hold time (transmission) t hd: dat 2.0 v v dd 5.5 v, c b = 100 pf, r b = 3 k 0 355 ns notes 1. the value must also be equal to or less than f mck /4. 2. set the f mck value to keep the hold time of sclr = "l" and sclr = "h". caution select the n-ch open drain output (v dd tolerance) mode for the sdar pin by using the port output mode register 0 (pom0). remarks 1. r b [ ]: communication line (sdar) pull-up resistance, c b [f]: communication line (sclr, sdar) load capacitance 2. r: iic number (r = 00) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bi t of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 22 of 28 simplified i 2 c mode connection diagram rl78 microcontroller user?s device sda00 scl00 sda scl v dd r b simplified i 2 c mode serial transfer timing sda00 t low 1/f scl t high t hd : dat scl00 t su : dat rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 23 of 28 2.6 analog characteristics 2.6.1 a/d converter characteristics (target ani pin : ani0 to ani3) (t a = ? 40 to +85 c, 2.4 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 8 10 bit v dd = 5 v 1.7 3.1 note 2 lsb overall error note 1 ainl 10-bit resolution v dd = 3 v 2.3 4.5 note 2 lsb 2.7 v v dd 5.5 v 3.4 18.4 s conversion time t conv 10-bit resolution 2.4 v v dd 5.5 v 4.6 18.4 s v dd = 5 v 0.19 note 2 %fsr zero-scale error note 1 e zs 10-bit resolution v dd = 3 v 0.39 note 2 %fsr v dd = 5 v 0.29 note 2 %fsr full-scale error note 1 e fs 10-bit resolution v dd = 3 v 0.42 note 2 %fsr v dd = 5 v 1.8 note 2 lsb integral linearity error note 1 ile 10-bit resolution v dd = 3 v 1.7 note 2 lsb v dd = 5 v 1.4 note 2 lsb differential linearity error note 1 dle 10-bit resolution v dd = 3 v 1.5 note 2 lsb analog input voltage v ain 0 v dd v notes 1. excludes quantization error ( 1/2 lsb). 2. this is the characteristic evaluat ion value plus or minus 3. these values are not used in the shipping inspection. 2.6.2 spor circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply rise time 4.08 4.28 4.45 v v spor0 power supply fall time 4.00 4.20 4.37 v power supply rise time 2.76 2. 9 0 3.02 v v spor1 power supply fall time 2.70 2.84 2. 96 v power supply rise time 2.44 2.57 2.68 v v spor2 power supply fall time 2.40 2.52 2.62 v power supply rise time 2.05 2.16 2.25 v detection supply voltage v spor3 power supply fall time 2.00 2.11 2.20 v minimum pulse width note t spw 300 s note time required for the reset operation by the spor when v dd becomes under v spdr . 2.6.3 power supply voltage rising slo p e ch aracteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply voltage rising slope s vdd 54 v/ms rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 24 of 28 2.6.4 data retention power supply voltage characteristics (t a = ? 40 to +85 c, vss = 0 v) parameter symbol conditions min. typ. max. unit data retention power supply voltage range v dddr 1.9 5.5 v caution data is retained until the power supply voltage becomes unde r the minimum value of the data retention power supply voltage range. note that da ta in the ram and resf registers might not be cleared even if the power supply voltage becomes under th e minimum value of the data retention power supply voltage range. rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 25 of 28 2.7 flash memory programming characteristics (t a = 0 to + 40 c, 4.5 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit code flash memory rewritable times notes 1, 2, 3 c erwr retained for 20 years. t a = + 85 c 1000 times notes 1. 1 erase + 1 write after the erase is regarded as 1 rewr ite. the retaining years are until next rewrite after the rewrite. 2. when using flash memory programmer. 3. these are the characteristics of the flash memory and the results obt ained from reliability testing by renesas electronics corporation. 2.8 dedicated flash memory programmer communication (uart) (t a = 0 to + 40 c, 4.5 v v dd 5.5v, v ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate 115,200 bps remark the transfer rate during flash memory programming is fixed to 115,200 bps. rl78/g10 chapter 2 electrical specifications r01ds0207ej0100 rev.1.00 apr 15, 2013 page 26 of 28 2.9 timing of entry to flash memory programming modes parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication settings are specified t suinit spor reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until an external reset ends t su spor reset must end before the external reset ends. 10 s how long the tool0 pin must be kept at the low level after an external reset ends t hd spor reset must end before the external reset ends. 1 ms reset tool0 <1> <2> <3> t suinit t hd t su <4> mode setting one-byte data <1> the low level is input to the tool0 pin. <2> the external reset ends (spor reset must end before the external reset ends.). <3> the tool0 pin is set to the high level. <4> setting of entry to the flash memory programming mode by uart reception. remark t suinit : the segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. t su : how long from when the tool0 pin is placed at the low level until an external reset ends (min. 10 s) t hd : how long to keep the tool0 pin at the low level from when the external reset ends rl78/g10 chapter 3 package drawings r01ds0207ej0100 rev.1.00 apr 15, 2013 page 27 of 28 3. package drawings 3.1 10-pin products r5f10y16asp, r5f10y14asp jeita package code renesas code p10ma-65-cac-2 6 10 1 v detail of lead end item dimensions a b c e f g h i j l m n d + 0.08 0.07 1.45 max. 0.50 0.13 0.10 k 0.17 p 3 + 5 3 (unit:mm) v w w a i f g e b k h j p u l t u v 0.25 max. w 0.15 max. 5 s c s n m d m t 2012 renesas electronics corporation. all rights reserved. note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 3.60 0.10 0.08 0.24 0.05 0.10 0.10 1.20 0.20 6.40 0.20 1.00 0.10 4.40 0.60 0.15 0.25 (t.p.) 0.65 (t.p.) 0.50 mass (typ.) [g] previous code plsp0010ja-a 0.05 p-lssop10-4.4x3.6-0.65 ? ? rl78/g10 chapter 3 package drawings r01ds0207ej0100 rev.1.00 apr 15, 2013 page 28 of 28 3.2 16-pin products r5f10y47asp, r5f10y46asp, r5f10y44asp jeita package code renesas code previous code mass (typ.) [g] p-ssop16-4.4x5-0.65 prsp0016jc-a p16ma-65-faa-2 0.08 16 1 8 s s s detail of lead end item dimensions d d1 e e a1 a a2 l1 l c x y zd bp 0.15 + 0.13 0.10 0.325 lp a3 3 5 3 (unit:mm) l1 a a2 a1 e y he c zd 5.00 0.15 5.20 4.40 0.20 0.20 6.40 0.05 + 0.125 1.725 max. 0.10 0.60 0.20 1.00 1.50 0.25 0.65 0.08 0.07 0.22 + 0.03 0.04 0.15 0.50 9 m bp x s he e d d1 l lp a3 2012 renesas electronics corporation. all rights reserved. c - 1 revision history rl78/g10 data sheet description rev. date page summary 1.00 apr 15, 2013 - first edition issued all trademarks and registered trademarks ar e the property of their respective owners. superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc. notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc ., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is po ssible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave different ly than bipolar or nmos dev ices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequ ate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does no t guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the re set signal is received. a reset operation must be ex ecuted immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the exte rnal power su pply and then the internal power supply. use of the reverse powe r on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. t he current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elemen ts. input of signals during the power off state must be judged separately for each device and according to re lated specifications governing the device. notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design. please be sure to implement possibility of physical injury, and injury or damage caused by fire in redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesas electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-owned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics liability for malfunctions or damages arising out of the safety measures to guard them against the life support devices or systems, surgical http://www.renesas.com 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 arcadiastrasse 10, 40472 d tel: +49-211-65030, fax: +49-211-6503-1327 sseldorf, germany dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics canada limited renesas electronics europe limited renesas electronics america inc. renesas electronics (china) co., ltd. renesas electronics (shanghai) co., ltd. renesas electronics europe gmbh renesas electronics taiwan co., ltd. renesas electronics singapore pte. ltd. renesas electronics hong kong limited renesas electronics korea co., ltd. renesas electronics malaysia sdn.bhd. sales offices ? 2013 renesas electronics corporation. all rights reserved. colophon 2.2 measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic electronics products or technology described in this document, you should comply with the applicable export control laws and |
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